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1/46 L7250 july 2001 this is preliminary information on a new product now in development. details are subject to change without notice. n 12v & 5v (10%) operation n register based architecture n 3 wire serial communication interface up to 33 mhz n bcd technology spindle motor controller n internal power device 0.9 ohm max value @ 125c (sink+source) n 2.5a peak current capability n st smoothdrive sinusoidal pwm commutation n dedicated adc for power supply voltage compensation n spindle current limiting via fixed frequency pwm of spindle power outputs at the smoothdrive pwm rate n synchronous rectification during pwm to reduce power dissipation n current sensing via external current sense resistor n inductive sense position start up driven by m processor n spindle braking during power down condition voice coil motor driver with ramp load/unload n internal power device 0.9 ohm max value @ 125c (sink+source) n 2a peak current capability n 15 bit linear dac for current command, with internal reference voltage n sense amplifier gain switch n class ab output stage with zero dead-band and minimal crossover distortion n ramp load and unload capability as well as constant voltage retract n external current sense resistor in series with motor. n high cmrr (>70db) and psrr (>60db) sense amp n external current control loop compensation n high bandwidth vcm current control loop capability n high psrr, low offset, low drift gm loop n vcm voltage mode, controlled by vcm dac n gm loop offset calibration scheme includes a comparator on the error amp auxiliary functions n 3.3v and 1.8v linear regulator controller n negative voltage regulator n internal isofet 0.1 ohm @125c n power monitor of 12v, 5v, 3.3v and 1.8v n shock sensor circuit takes inputs from piezo or charging element n 10 bit adc with 4 muxed inputs n thermal sense circuit and over temperature shut down n charge pump boost voltage generator for high side gate drive n analog pins available to enter signals to be converted by the internal adc description L7250 is a power ic for driving the spindle and vcm motors, suitable for 5v & 12v application. the spindle system includes integrated power fets which are driven using st's smoothdrive pseudo-si- nusoidal commutation technology. the voice coil mo- tor (vcm) system includes integrated power fets, as well as ramp load and unload capability. linear 3.3v and1.8v voltage regulators are included, as well as a negative regulator. power monitoring of vcc5, vcc12, and of the two positive voltage regulators is also included.L7250 uses a 3 wire serial interface: s_data, s_clk and s_enable tqfp64 ordering number: L7250 product preview 5v & 12v spindle and vcm motors driver
L7250 2/46 pin connection (top view) pin description n pin v description 1 vcv1 s12 12v power supply 2 vcv2 s12 12v power supply and por sensing threshold 3 vcmp1 o12 vcm positive output 4 vcmp2 o12 vcm positive output 5 vcmgnd1 gnd vcm power ground 6 vcmgnd2 gnd vcm power ground 7 cposc o12 charge pump oscillator 8 vcc5 s5 5v power supply 9 dig_gnd gnd digital & switching regulator ground 10 n_drv o5 neg reg ext fet gate driver 11 n_feed i5 neg reg feedback 12 n_comp io5 neg reg error output 04 05 06 07 08 09 10 11 12 13 14 15 16 03 01 02 20 21 22 23 24 25 26 27 28 29 30 31 32 19 17 18 52 53 54 55 56 57 58 59 60 61 62 63 64 51 49 50 45 44 43 42 41 40 39 38 37 36 35 34 33 46 48 47 vcv1 vcv2 vcmp1 vcmp2 vcmgnd1 vcmgnd2 cposc vcc5 dig_gnd n_drv n_feed n_comp 25_base 25_feed 33_base 33_feed rsen2 rsen1 vcmn2 vcmn1 vcmgnd4 vcmgnd3 sns_n sns_p sns_out err_out err_in dac_out sen sclk sdata sysclk cpor npor cbrake agnd vref25 zc skin skout skfin skfout skdout timer1 calcoarse adaux vcmbemf te s t vboost cposch ct outu2 outu1 rsen4 rsen3 outv2 outv1 vcv3 vcv4 vm2 vm1 outw2 outw1 rsense
3/46 L7250 13 25_base o5 reg 1.8v ext npn base 14 25_feed i5 reg 1.8v feedback 15 33_base o5 reg 3.3v ext npn base 16 33_feed io5 reg 3.3 v feedback 17 cpor io5 por delay capacitor 18 npor o5 por output signal 19 cbrake io5 spindle brake capacitor 20 agnd gnd analog gnd 21 vref25 io5 2.5v reference 22 zc o5 spindle zero crossing 23 skin i5 shock sensor input 24 skout o5 shock sensor 1st opamp output 25 skfin i5 shock sensor filter input 26 skfout o5 shock sensor filter output 27 skdout o5 shock sensor output 28 timer1 io5 timer 1 for unload procedure 29 calcoarse i5 vcm bemf coarse calibration 30 adaux i5 auxiliary input for the adc 31 vcmbemf o5 vcm bemf processor output 32 test io5 used for testing porpouse (*) 33 sen i5 serial enable 34 sdata io5 serial data 35 sysclk i5 system clock 36 sclk i5 serial clock 37 dac_out o5 vcm dac output 38 err_in i5 vcm error opamp input 39 err_out o5 vcm error opamp output 40 sns_out o5 vcm sense opamp output 41 sns_p i12 vcm sense opamp positive input 42 sns_n i12 vcm sense opamp negative input 43 vcmgnd3 gnd vcm power ground pin description (continued) n pin v description
L7250 4/46 (*) used also to set the ic power supply application. if this pin is pull-up externally the L7250 became a 5v application s = supply ; io = input/output ; i = input ; o = output ; gnd = ground. 44 vcmgnd4 gnd vcm power ground 45 vcmn1 o12 vcm negative output 46 vcmn2 o12 vcm negative output 47 rsen1 o12 spindle power sensing resitor 48 rsen2 o12 spindle power sensing resitor 49 rsense i5 spindle sensing resistor input 50 outw1 o12 spindle phase c output 51 outw2 o12 spindle phase c output 52 vm1 io12 vmotor 53 vm2 io12 vmotor 54 vcv4 s12 12v power supply 55 vcv3 s12 12v power supply 56 outv1 o12 spindle phase b output 57 outv2 o12 spindle phase b output 58 rsen3 o12 spindle power sensing resitor 59 rsen4 o12 spindle power sensing resitor 60 outu1 o12 spindle phase a output 61 outu2 o12 spindle phase a output 62 ct i12 spindle central tap 63 cposch io20 charge pump diodes connection 64 vboost io20 charge pump voltage pin description (continued) n pin v description
5/46 L7250 electrical characteristcs absolute maximum ratings symbol parameter value unit vcv1,vcv2,vcv3,vcv4 14 v vcc5 maximum voltage 6 v outu1,outu2,outv1,outv2,outw1,outw2 vcmp1,vcmp2,vcmn1,vcmn2 vm1,vm2 -1v to 16 v digital input voltage -0.3 to vcc5 v operating free-air temperature 0 to 70 c storage temperature -55 to 150 c electrical characteristcs power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit power monitor, supply currents, etc. icc5 vcc5 operating current spindle and vcm enabled, no load 9ma ivcv vcv + vret operating current spindle and vcm enabled, no load 44 ma charge pump voltage booster vboos t charge pump output voltage vcv = 12v iload = 5ma 18.5 v vboos tfreq switching frequency 1 mhz power monitor vt5 vcc5 threshold 4.0 4.175 4.35 v vt12 vcc12 threshold 9 9.5 10 v hv5 vcc5 hysteresis 40 100 160 mv hv12 vcc12 hysteresis 100 200 300 mv vt33 v33 threshold 2.7 2.8 2.9 v hv33 v33 hysteresis 20 40 60 mv vt18 v18 threshold (at pin 25_feed) 1.07 1.12 1.17 v hv18 v18hysteresis 25 50 75 mv npor low npor low level output voltage vcv > 4.5v iol = 5ma 0.75 v
L7250 6/46 npor pull npor internal pull_up resistor to v33 6kohm cpor ic cpor charging current vout = 0v 5 ua cpor low cpor low level output voltage vcv > 4.5v iol = 1ma 50 mv vref25 2.5v reference voltage -5% 2.5 +5% v thermal warning and thermal shutdown t warn thermal warming temperature characterized, tested by correlation. 130 140 150 c tsoff thermal shutdown temperature characterized, tested by correlation 150 165 180 c thys thermal hysteresis valid for both temperature thresholds 20 25 30 c vm isolation fet isor rds on @ 125c , i=2.5a 0.1 ohm isoi continuous current 2.5 a spindle driver section power stage rds(on) total output on resistance (source + sink) @ 125c, i=2.5a 0.9 w idsx output leakage current -200 -500 m a ctlkg centarl tap leakage 1 m a diodefw clamp diode forward voltage if = 2.5a 0.6 1.2 v slew output slew rate outx 10% to 90% reg04h b7b6b5 = 011 40 v/ m s back emf comparator vie common mode input voltage range. guaranteed by design 0 vm v vr input voltage range where output shall not invert. guaranteed by design -1 vm+1 v bemfoff bemf input offset ct = 6v -15 +15 mv bemfhy bemf hysteresys ct = 6v 50 mv spindle current limiting iin rsense input bias current. 0 < vin < 3.3v 1 m a curoff comparator offset -15 +15 mv electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
7/46 L7250 curdacr dac resolution 3 bit cur dac_l dac output reg04h b4b3b2 = 000 250 mv cur dac_h dac output reg04h b4b3b2 = 111 600 mv cur lin dac linearity -10 +10 mv cbrake icbrake vcbrake leakage vcbrake=5v 1 m a vcm section current sense amplifier vts common mode input voltage range. gbd - not tested -0.6 vm+1 v sns _vof f input offset voltage -12 12 mv sns_gain0 differential voltage gain0 reg09h b7 = 0 -5% 4.5 +5% sns _gain1 differential voltage gain1 reg09h b7 = 1 -5% 16 +5% sns_low sns_high vsense output saturation voltage iload=+/-1ma vin_diff=+/- 500mv 4.75 250 mv v sns_slew output slew rate cload=50pf 1 v/s sns_band -3db bandwidth guaranteed by design 200 400 khz sns _cmrr common mode rejection ratio f < 10 khz, tested at dc only cmrr=a v diff/av cm 70 db sns _svrr supply voltage rejection ratio vcv f < 10 khz, tested at dc only 60 db error summing amplifier err _gain voltage gain no load 60 db err _band unity gain bandwidth guaranteed by design 4 mhz err _slew output slew rate cload=50pf 1.5 v/ m s err _ibias input bias current 1 m a err _off input offset voltage -10 0 10 mv err_svrr supply voltage rejection ratio f < 10 khz, tested at dc only 60 db err _clamp low low output (clamp) voltage isink = 1 ma, referred to vref25 tbd v electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
L7250 8/46 err _clamp high high output (clamp) voltage isource = 1ma, referred to vref25 tbd v vcm output drivers pwr_gain power amplifier differential gain. i o = 1a, rload = 8 w 14 15 16 v/v rds(on) total output on resistance (source + sink) @ 125c, i=2a .9 w pwr_lkg output leakage current 600 ua diodefw clamp diode forward voltage if = 2a 0.6 1.2 v thd total harmonic distortion characterized no tested 1 % pwr_slew vcmn or vcmp slew rate r l = 8 ohms 1 v/us pwr_b and power amp -3db bandwidth driving errout = vdacref, guaranteed by design 250 500 khz icross static shoot-through current guaranteed by design 0 ma vcm current control loop static and dynamic characteristics ivcmoff total offset current rs=0.2 -75 75 ma divcmoff total offset current drift temperature coefficient guaranteed by design .2 ma/ o c gm_psrr gm loop vsrr of vcv -1 1 ma/v vcm linear dac dac_res resolution 15 bit dac_out full scale output voltage wrt vdacref 0.96 1 1.04 v dac_off mid-scale error wrt vdacref -12 12 mv dac_dnl differential non linearity guaranteed monotonicity 1 lsb dac_inl integral non linearity 64 lsb dac_co nvt conversion time 90% from 3fffh to 0020h 3 m s vcm load/unload adc adc_res resolution 10 bit adc_dnl differential non linearity 1 lsb adc_inl integral non linearity 3 lsb adc_co nvt conversion time 40 adc clock cycles electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
9/46 L7250 adc auxiliary input aux_ran ge0 input range 0 reg06h b3 = 0 referred to vref25 1 v aux_ran ge1 input range 1 reg06h b3 = 1 referred to vref25 2.25 v aux_ibias input bias -100 100 m a vcm voltage amplifier volt_gain voltage gain 0.165 v/v volt_off input offset -15 +15 mv volt _cmrr common mode rejection ratio f < 10 khz, tested at dc only cmrr=a v diff/av cm 46 db volt _svrr supply voltage rejection ratio f < 10 khz, tested at dc only 60 db bemf processor amplifier calcoar sein calcoarse voltage input range 0.5 2 v gain1 first stage gain vcontrol = 1.25 v 1.91 v/v gain2 second stage gain 16 v/v offset residual input offset after calibration vcontrol = 1.25v (measured between vcmn and sns_p pins) -3 +3 mv rout bemf amp output resistance (pin 31) 500 ohm uload @ por timer1_v timer1 charging voltage 2.5 v timer1_i timer1 discharging current 2 m a timer1_t timer1 low threshold 0.2 v voltage regulators 1.8 and 3.3 linear regulator v18 feed 1.8v feedback voltage -5% 1.25 +5% v v33 out 3.3v output voltage -5% 3.3 +5% v electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
L7250 10/46 v18 idrive v33 idrive output base current drive 15 ma negative regulator freq0 oscillator frequency default configuration 500 khz freq1 oscillator frequency testregister = 00001001 or = 00101001 1 mhz vouth high level output voltage tbd v voutl low level output voltage tbd v vneerr offs feedback input offset -10 10 mv vnegerr bias feedback input bias 0 1 m a vneg_err _cmrr common mode rejection ratio f < 10 khz, tested at dc only cmrr=a v diff/av cm 46 db vneg_err _svrr supply voltage rejection ratio vcv f < 10 khz, tested at dc only 60 db shock sensor skigain0 input opamp gain0 reg02h b7 = 0 10 v/v skigain1 input opamp gain1 reg02h b7 = 1 80 db skioff input opamp offset -15 +15 mv skiinput input opamp input impedance reg02h b7 = 0 10 mohm skfgain filter opamp open loop gain 80 db skfband filter opamp unity gain bandwidth guaranteed by design 5 mhz skfoff filter opamp offset voltage -10 +10 mv skothh0 output window comparator vthhigh referred to vref25 ; reg02h b6 = 0 200 mv skothh1 output window comparator vthhigh referred to vref25 ; reg02h b6 = 1 500 mv skothl0 output window comparator vthlow referred to vref25; reg02h b6 = 0 200 mv skothl1 output window comparator vthlow referred to vref25; reg02h b6 = 1 500 mv electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
11/46 L7250 1 serial port the serial port is a bidirectional three pin interface, using sdata, sclk and sen to address and communicate with sixteen 8 bit registers in the L7250. these registers include the status register, spindle control registers, vcm control registers, sinewave drive registers, and test mode register. these registers are cleared to zero at power up. 1.1 default comunication modes setting (bit 7, reg05h ) = 0 after the sen falling edge, the internal state machine is waiting for the first sclk falling edge. this means that if the sclk line starts from an high level the first falling edge, respecting the setup time tefcf, is considered, and is used to read the r/w bit. during a writing process the internal state machine must see 16 sclk falling edges to validate the operation. the write mode is started if the r/w bit is low on the first falling edge of sclk. the read mode is started if the r/w bit is high on the first falling edge of sclk. the id, address, and data are all then subsequently read by the L7250 on the falling edges of sclk. (see figure 1) the microcontroller has to read the data on the falling edge of the sclk signal. after the hold time (tedh) the data line switches to the next data without a tri-state phase.during a read mode the last address bit is read by L7250 on the eighth falling edge of sclk. the internal state machine then turns the sdata bit around for the L7250 to assume control at the next sclk rising edge (the first rising edge after the 8th sclk falling edge). serial port voh logic output voltage high ioh=1ma 2.7 v vol logic output voltage low iol=1ma 0.5 v vih logic input high iih=1ua 2.2 v vil logic input low iil=-1ua 0.5 v iih logic high input current internal pulldown resistor vin = 3.3v 33 m a iil logic low input current -1.00 m a electrical characteristcs (continued) power supply [vcc5 & vcv] vcc5 = 5v 10%, vcv = 12v 10%. t amb = 25c (unless otherwise specified) symbol parameter test condition min. typ. max. unit
L7250 12/46 figure 1. default serial port timing diagram (bit 7, reg05h = 0) note1: during writing process L7250 latches the data on the sclk falling edge (the asic is writing on the sclk rising edge) note2: during reading process L7250 takes the bus control on the next sclk rising edge after the 8th sclk falling edge the L7250 write the data on the sclk falling edge respecting the data hold time (tedh) note3: the id number for the L7250 is id1=id2=id3=1 r w id2 id2 id2 a2 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 id2 id2 id2 a2 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdata (write) sdata (read) sen sclk tefcf teh tcc tch tcl tcfer tcrer tcdd tedh L7250 takes bus control tcds tcdh tdly
13/46 L7250 1.2 default serial port timing table 1.3 inverted clock comunication modes (bit 7, reg05h) = 1 to set the bit7, reg05h to 1, entering this different comunication mode, a writing process using the default co- munication protocol (see the above paragraph) must be used. after the sen falling edge, the internal state machine is waiting for the first sclk rising edge. this means that if the sclk line starts from a low level the first rising edge, respecting the setup time tefcr, is considered, and is used to read the r/w bit. the internal state machine must see 16 sclk rising edges to validate the write operation. the write mode is started if the r/w bit is low on the first rising edge of sclk. the read mode is started if the r/w bit is high on the first rising edge of sclk. the id, address, and data are all then subsequent- ly read by the L7250 on the rising edges of sclk (see figure 2). the microcontroller has to read (latch) the data on the falling edge of the sclk signal. L7250 presents the data on the sclk rising edge. during a read mode the last address bit is latched by the L7250 on the eighth rising edge of sclk. the internal state machine then turns the sdata bit around for the L7250 to assume control at the next sclk falling edge (the first falling edge after the 8th sclk rising edge). symbol parameter min max unit tcc serial clock period 30 ns tch serial clock high time 13 ns tcl serial clock low time 13 ns tcds serial data setup time to clock falling edge (write mode) 5 ns tcdh serial clock falling edge to serial data hold time (write mode) 4 ns tedh serial clock falling edge to serial data hold time (read mode) 5 ns tcdd serial data setup time to clock falling edge (read mode) 5 ns tel serial enable low time 490 ns teh serial enable high time 30 ns tefcf serial enable falling edge to serial clock falling edge 17 ns tcfer serial clock falling edge to serial enable rising edge 17 ns tdly sdata turn around delay time 0 ns note 1: all specifications with respect to 50% of signal switching thresholds note 2: reading mode tested at max 20mhz
L7250 14/46 figure 2. inverted clock serial port timing diagram (bit 7, reg05h = 1) note1: during writing process L7250 latches the data on the sclk rising edge (the asic is writing on the sclk falling edge) note2: during reading process L7250 takes the bus control on the next sclk falling edge after the 8th sclkris- ing edge the L7250 write the data on the sclk rising edge and it is expecting the asic to latches the data on the sclk falling edge note3: the id number for the L7250 is id1=id2=id3=1 r w id 2 id2 id2 a2 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 id 2 id2 id2 a2 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sdata (write) sdata (read) sen sclk tefcr tel teh tcc tch tcl tcrer tvld tedh L7250 takes bus control tcds tcdh tdly
15/46 L7250 1.4 inverted clock serial port timing table symbol parameter min max unit tcc serial clock period 30 ns tch serial clock high time 13 ns tcl serial clock low time 13 ns tcds serial data setup time to clock falling edge (write mode) 5 ns tcdh serial clock falling edge to serial data hold time (write mode) 4 ns tedh serial clock falling edge to serial data hold time (read mode) 5 ns tvld serial clock rising edge to sdata stable time (read mode) cload=5pf (see note2) cload=50pf (see note2) 11 15 ns ns tel serial enable low time 490 ns teh serial enable high time 30 ns tefcr serial enable falling edge to serial clock rising edge 17 ns tcrer serial clock rising edge to serial enable rising edge 17 ns tdly sdata turn around delay time 0 ns note 1: all specifications with respect to 50% of signal switching thresholds note 2: in reading mode the clock frequency is limited by this parameter; in fact the min serial clock high time is defined by (tvld+tasu) where tasu = min asic setup time
L7250 16/46 table 1. register map addr b7 b6 b5 b4 b3 b2 b1 b0 name mnemoni c attributes 00h spncurrsi gn vcmcalout zcbad thshutdown thwarn rev2 rev1 rev0 sr status readonly 01h rlvoltage1 [1] rlvoltage1 [0] rlvoltage2 [1] rlvoltage2 [0] rltimer[2] rltimer[1] rltimer[0] nobrake vcm1 vcm rlreg read/write 02h shockconf shockth[0] rltoffbrake [1] rltoffbrake [0] rlcalib[3] rlcalib[2] rlcalib[1] rlcalib[0] vcm2 vcmrl reg read/write 03h bemfoffcal vcmstate2 vcmstate1 vcmstate0 spstate3 spstate2 spstate1 spstate0 ctr1 sp&vcmst ate read/write 04h spslew2 spslew1 spslew0 curdac2 curdac1 curdac0 pwmmask1 pwmmask0 ctr2 control read/write 05h spiprot m3 m2 m1 m0 tsden vnegen sken ctr3 control read/write 06hw4w3w2w1w0 preadc(1) preadc(0) presmo ctr4 control read/write 07h loadcp advance ffwen to4 to3 to2 to1 to0 ctr5 control read/write 08h kv7 kv6 kv5 kv4 kv3 kv2 kv1 kv0 kvr kval read/write 09h gainswitch dac14 dac13 dac12 dac11 dac10 dac9 dac8 dar1 dac reg 1 read/write 0ah dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 dar2 dac reg 2 read/write 0bh adc_data (9) adc_data (8) adc_data (7) adc_data (6) adc_data (5) adc_data (4) adc_data (3) adc_data (2) adr adc reg readonly 0ch adc_data (1) adc_data (0) adc_res _addr(1) adc_res _addr(0) adcrange adc_ch_ addr(1) adc_ch_ addr(0) adc_start adr adc reg read/write 0dh reser ved reser ved reserved reserved reserved reserved reserved reserved read/write 0eh reser ved reser ved reserved reserved reserved reserved reserved reserved read/write 0fh test7 test6 test5 test4 test3 test2 test1 test0 test test read/write
17/46 L7250 table 2. register map content description (continued) bit spi field name content register sr, address: 00h [2:0] rev[2:0] revision number of the device, set internally [3] thwarn thermal warning [4] thshutdown thermal shutdown [5] zcbad signals a problem with spindle speed loop synchronism [6] vcmcalout vcm error output in calibration mode [7] spncurrsign spindle current sign to implement adaptive torque optimizer control register vcm1, address: 01h [0] nobrake 0=vcm active brake phase enabled 1= vcm active brake phase disabled [3:1] rltimer[2:0] 000 = only unload1 is enabled 001 = threshold set to 0.4v 010 = threshold set to 0.8v 011 = threshold set to 1.2v 100 = threshold set to 1.6v 101 = threshold set to 2v 110 = threshold set to 2.4v 111 = only unload2 is enabled [5:4] rlvoltage2[1:0] selects between 4 values of unload voltage in unload2 phase: 00 = 1v 01 = 1.125v 10 = 1.250v 11 = 1.375v [7:6] rlvoltage1[1:0] selects between 4 values of unload voltage in unload1 phase: 00 = 0.375v 01 = 0.5v 10 = 0.625v 11 = 0.75v register vcm2, address: 02h [3:0] rlcalib[3:0] 0111 = 29.4% 0110 = 25.2% 0101 = 21% 0100 = 16.8% 0011 = 12.6% 0010 = 8.4% 0001 = 4.2% 0000 = 0% 1111 = -4.2% 1110 = -8.4% 1101 = -12.6% 1100 = -16.8% 1011 = -21% 1010 = -25.2% 1001 = -29.4% 1000 = -33.6%
L7250 18/46 [5:4] rltoffbrake[1:0] selects the duration of toff (ton) active brake phase: 00 = 300usec 01 = 400usec 10 = 500usec 11 = 600usec [7] skockconf selects the shock sensor application 0 = piezo element 1 = charging element [6] skockth[0] selects the shock sensor threshold 0 = vref +/- 200mv 1 = vref +/- 500mv register ctr1, address: 03h [3:0] spstate[3:0] 0000 = clcoast 0001 = olcoast 0010 = olsix 0011 = olsin 0100 = olbrake 0101 = indsense 0110 = clsix 0111 = clsin 1000 = clbrake [6:4] vcmstate[2:0] possible states for the vcm: 000 = unload/retract 001 = tri-state 010 = brake 011 = enable current mode 100 = enable voltage mode 101 = offset calibration 110 = confirm the previous state 111 = confirm the previous state [7] bemfoffcal vcm bemf processor offset calibration register ctr2, address: 04h [1:0] pwmmask[1:0] selects the length of the mask over pwm rising edge: 00 = 2 us 01 = 4 us 10 = 6 us 11 = 8 us [4:2] currdac[2:0] selects the voltage threshold for the spindle current limiter: 000 = 250mv 001 = 300mv 010 = 350mv 011 = 400mv 100 = 450mv 101 = 500mv 110 = 550mv 111 = 600mv table 2. register map content description (continued) bit spi field name content
19/46 L7250 [7:5] spslew[2:0] 000 = 10 v/us 001 = 20 v/us 010 = 30 v/us 011 = 40 v/us 100 = 50 v/us 101 = 60 v/us 110 = 70 v/us 111 = 80 v/us register ctr3, address: 05h [0] sken 0 = shock sensor output no latched 1 = shock sensor output latched (to clear the latched information a transition 1 -> 0 -> 1 is necessary) [1] vnegen 0 = negative regulator disabled 1 = negative regulator enabled [2] tsden 0 = thermal shutdown disabled 1 = thermal shutdown enabled [6:3] m[3:0] masking while sensing zc, expressed in terms of half samples after window opening in terms of electrical degrees the single mask step is 3.75. [7] spiprot 0 = default protocol 1 = inverted sclk protocol register ctr4, address: 06h [0] presmo 0 = spindle clock is system clock divided by two (ffwdadc clock is system clock divided by 8) 1 = spindle clock is system clock (ffwdadc clock is system clock divided by 4) [2:1] preadc[1:0] 00 = sleep mode 01 = adc clock is system clock divide by 4 10 = adc clock is system clock divide by 2 11 = adc clock is system clock [7:3] w[4:0] windowing while sensing zc, expressed in terms of half samples before to value in terms of electrical degrees the single window step is 3.75. register ctr5, address: 07h [4:0] to[4:0] coarse and fine section of phase shift, applied for torque optimization. in terms of electrical degrees the torque optimizer single step is 0.937 electrical degrees. [5] ffwen 0 = power supply compensation for spindle disabled 1 = power supply compensation for spindle enabled [6] advance 0->1 increments by one the current sample position [7] loadcp 0->1 enables load of to value as the current sample position register kvr, address: 08h [7:0] kv[7:0] kval factor for speed loop control table 2. register map content description (continued) bit spi field name content
L7250 20/46 register dar1, address: 09h [6:0] dac[14:8] 7 msb for vcm dac [7] gainswitch 0 = gain voltage of the vcm sense amplifier equal to 4.5 v/v 1 = gain voltage of the vcm sense amplifier equal to 16 v/v register dar2, address: 0ah [7:0] dac[7:0] 8 lsb for vcm dac register adr, address: 0bh [7:0] adc_data[9:2] 8 msb output data from adc conversion register adr, address: 0ch [0] adcstart 0-> 1 starts a new adc conversion [2:1] adc_ch_addr[1:0] channel whose conversion is required 00 = vcm current sense amplifier output 01 = vcm voltage amplifier output 10 = vcm bemf 11 = auxiliary channel (external pin) [3] adcrange 0 = the 4 signals enter directly (maintaining the proper dynamic range) the adc block 1 = the 4 signals are scaled down to the adc dynamic range [5:4] adc_res_addr[1:0] channel whose result conversion is currently present in adc_data register adr, address: 0dh 0dh [7:0] reserved register adr, address: 0eh 0eh [7:0] reserved register adr, address: 0fh 0fh [7:0] test[7:0] test register table 2. register map content description (continued) bit spi field name content
21/46 L7250 2 spindle motor controller figure 3. 2.1 spindle smoothdrive functionality L7250 utilizes st's proprietary smoothdrive commutation algorithm. smoothdrive is a voltage mode pseudo- sinusoidal spindle drive scheme where the duty cycles of the three windings are modulated to form sinusoidal voltages across each winding. the system determines the shape and amplitude of the driving voltages in a completely digital manner. 2.2 sysclk the smoothdrive system clock comes through the sysclk pin. the system expects either 33mhz or 16.5mhz on this pin, and needs 16.5mhz internally. a sysclk divide by two can be enabled by a spi register bit presmo to accomodate a 33mhz external clock. 2.3 smoothdrive wave shape the basic smooth drive wave shape is stored in digital memory. a voltage profile designed to reduce switching losses and increase the voltage headroom has been implemented. essentially, two phases are pwm'ed, while the low side driver of the third phase is on at 100% duty cycle. the pwm duty cycles are modulated in such a way as to result in sinusoidal currents on all 3 motor phases. driving in this manner, as opposed to driving true sinusoids on all three phases, results in improved headroom and efficiency, approaching that of conventional 6 state commutation. the system is phase locked to the motor by sensing one bemf zero crossing on one winding, once per electrical vm hgu motu lgu fet gate drive vm hgv motv lgv fet gate drive vm hgw motw lgw fet gate drive xx smoothdrive profile memory/ logic memory address counter ( n=48 ) digital multiplier counter & comparators xx ct ap window mask pwm mask zero crossing period counter 16+4 bit fscan counter zc tc fscan bemf comp. current limit comp. advance bit olsix/olsin or clsix/clsin kval register kval coarse phase advance bits fine phase advance bits sysclk 16.5mhz spindle motor loadcp bit smoothdrive raw duty cycle smoothdrive modulated duty cycle time domain duty cycle signals spsenh vm adc start-of-count supply voltage compensation mask registers window tristate cmd 6 state or sine mode cur dac
L7250 22/46 cycle. a window is opened up in that winding, and it is tri-stated to allow sensing of the zero crossing. the width of the window opening is programmable, and can be made very small in steady state. a frequency locked loop keeps the wave shape in sync with the motor speed. the system is entirely digital, requiring no external com- ponents. the smoothdrive wave shape is sync with the motor. it divides the electrical period, from one zero crossing to the next, into 48 evenly spaced sample periods. for each sample period, the driving duty cycle is defined for each motor phase by a table in the smoothdrive logic. the memory address counter sequences the samples through the cycle, and is clocked n times per cycle. the following describes how the frequency locked loop system works: there are n sine wave samples per electrical rev. n=48 for this design. each electrical period (from one zc to the next) is measured by a timer with an effective frequency of fsysclk/ 48, resulting in a measured zero crossing period tc. the timer does not actually run at fsysclk/48 - the reso- lution is more like fsysclk/3. the fscan counter is a down counter preloaded with tc, and running at fsysclk. the fscan counter puts out a pulse each time it hits zero, then it resets to tc and counts down again. this cycle occurs n (48) times per electrical cycle. thus, the fscan counter divides the electrical cycle into n evenly spaced samples based on the previous tc. the pulse signal out of this block, that occurs 48 times per electrical period, is called fs- can. the memory address counter counts fscan pulses, and tells the profile logic which full scale duty cycle val- ues to use for each smoothdrive sample period. 2.4 pwm rate the pwm rate is unrelated to the smoothdrive sample rate. the minimum pwm rate is 32.2khz with 16.5mhz spindle system clock, defined by (fsys/512). the spin system clock is sysclk or sysclk/2, chosen via serial port (sysclk/2 is the default at power up). 9 bits of resolution define the duty cycle at each sample period. the pwm counter is reset at the beginning of each electrical cycle (at the zc). the pwm duty cycle is defined for each of the two chopping phases by comparing the appropriate duty cycle values to the counter. the duty cycle values are the result of multiplying values in the smoothdrive waveform table by the amplitude value kval coming from spi. 2.5 supply voltage compensation via adc the smoothdrive system is a voltage mode drive scheme. without compensation, the spindle drive amplitude would be a proportion of the motor supply voltage. L7250 implements a supply voltage compensation scheme whereby the drive amplitude is indipendent on motor supply voltage. an internal 6 bit adc reads the motor supply voltage variation (+/-10%), and the applied duty cycle is modified to keep the applied voltage constant. a side effect is that the pwm frequency will be changed as well as the duty cycle. the adc runs on a 4mhz clock derived from the sysclk (it is divided by 8 if the presmo bit is set to zero else it is divided by 4). the conversion results affects the pwm counter once per pwm cycle, nominally 32 khz. 2.6 bemf comparator hysteresis since only one polarity zc is detected, the bemf comparator hysteresis no longer needs to contribute a time offset. the hysteresis is zero on the significant edge, and is engaged on the other edge. thus, larger values of hysteresis can be used to provide noise immunity at low speed while coasting, without affecting zc timing. hysteresis of 50mv provides adeguate sensitivity for detecting motion startup, while improving noise immunity when the motor is moving very slow or is stationary. 2.7 startup algorithm description L7250's spindle motor startup is controlled by firmware, and consists of four distinct phases: inductive position
23/46 L7250 sense, to determine rotor position, open loop commutation, which accelerates the motor to build up bemf, synchronization , to measure motor speed and position, initializing the smoothdrive system, and closed loop smoothdrive commutation, the normal synchronous commutation mode to accelerate and run at speed. 2.7.1 inductive position sense inductive position sensing is achieved through a firmware routine that measures the current rise time in each of the six possible states (six steps profile), and uses this information to determine the rotor position. the six steps profile still comes from the profile memory that contains 48 samples, but in this case there are only six different configuration, each of them repeated eight times; the linear scansion of the memory one sam- ple at a time gives a new six step configuration every eight increments. before any operation can be done, the firmware routine must set the kval value present in spi to the maximum value (*1) , to saturate the pwm signals given to the motor, and put the memory address counter in a known position (*3); this is done keeping the motor in olcoast (*2) state and asserting a loadcp command (*4) to load the content of the torque optimizer related spi register into the memory address counter. at this point, the present six steps configuration can be energized through the indsense state (*5) , waiting for the current to reach the threshold programmable via spi (*6); the current limiting comparator will be triggered by this condition, and it's output will be visible at zc pad. the current rise time will be measured and stored from the asic (*7) . the device automatically limits the pwm signals for the three phases to limit the current, but the currents in the windings must be recirculated from firmware putting the motor in olcoast (*8) state. a burst of eight advance signals (*9) must be asserted from spi to reach the next configuration in the profile memory, then the procedure can be repeated. each winding can be excited more than one time, to average the measurements, and at the end of the sensing sequence the asic decides the rotor position. figure 4. inductive sense routine set kval write reg.08h kv[7:0] = 11111111 measure current rise time by reading the zc (pin 22) set olcoast write reg.03h spstate[3:0] = 0001 set torque optimizer write reg.07h to[4:0] = 00000 set load coarse phase write reg.07h loadcp = 1 set advance write reg.07h advance = 1 set inductive sense write reg.03h spstate[3:0] = 0101 store the measured current rise time & nph associated set olcoast write reg.03h spstate[3:0] = 0001 start inductive sense routine nadv=0 , nph=0 nadv=8 inc nadv inc nph nph = 48 compare the six measured rise time to define the rotor position exit inductive sense routine wait for current decay nadv=0 zc=0 zc=1 no yes yes no (*1) (*2) (*3) (*4) (*5) (*6) (*7) (*8) (*9)
L7250 24/46 2.7.2 open loop commutation after position sense is complete, the microcontroller commutates the motor following a constant acceleration profile until sufficient bemf is developed to reliably measure it. the starting position of the open loop commutation, determined by the position sense routine, is set up by first initializing the memory address counter using loadcp (*1), then clocking advance (*2) the appropriate number of times (8 pulses per 6 state position). the spindle state will be olcoast while setting the initial state. then, drivers are enabled in either ol_six or ol_sin modes (*3) , depending on whether 6 state or sine mode open loop commutation is desired. once the motor is accelerated up to an appropriate speed (*4) , the motor is tri-stated by transitioning to the olcoast (*5) and then clcoast states, as described below, to synchro- nize the smoothdrive system to the motor. figure 5. open loop commutation 2.7.3 synchronization to smoothdrive commutation when the open loop commutation is complete, the drivers are put in olcoast mode, and after a delay for set- ting the bemf sampling period, clcoast is asserted, so that a zc period (tc, the time between two bemf zero crossings) can be detected and measured. the bemf sampling period is set in olcoast (*1) and after a delay (30 usec ) a load cp (*2) is asserted. after a delay of time tc0 (300usec suggested) another load cp is asserted (*3); this initializes the electrical period for bemf sampling. once pregrammed the transition to clcoast (*4) , the bemf is sampled at the rate of tc0 to look for two consecutive low readings (in anticipation of the low->hi zero crossing transition (*5) ). after the first zc rising edge, the bemf sampling period is refreshed to tc0 value. if two consecutive zc edges are detected (*6), then after the last rising edge the smoothdrive commutation is synchronized with the motor rotor position and it is ready to be programmed in closed loop commutation . at least two zcs must be observed before transitioning to closed loop spinup (clsix or clsin) (*7a or *7b) . this ensures that the smoothdrive circuitry is synchronized to the spindle motor. set load coarse phase write reg.07h loadcp = 1 (*1) set advance write reg.07h advance = 1 nadv=nalign inc nadv start open loop commutation nadv=0 , i=0 note2: nalign is received from the inductive sense routine indicating the rotor position alignement accelerate in sine or six set open loop sine write reg.03h spstate[3:0] =0011 set open loop six write reg.03h spstate[3:0] =0010 set advance write reg.07h advance = 1 wait the end of ramp_delay[ i ] inc i i = ramp_steps set olcoast write reg.03h spstate[3:0]=0001 exit open loop commutation (*2) (*3) (*4) (*5) sine six note1: spstate[3:0] condition has been set in olcoast by the inductive sense routine
25/46 L7250 figure 6. synchronization to smooth drive commutation 2.7.4 closed loop commutation during closed loop commutation, the motor is driven following the smooth driver wave shape (or the traditional six step profile). to keep sync, each electrical cycle a winding of the spindle motor (phase u) is tri-stated, for a programmable (via spi) window (w), to sense for the zc occurrence; to mask the current flyback time a mask- ing time is applied starting from the opened window for a certain number m of samples (settable via spi). due to the fact that the motor winding is driven in voltage mode a control of the phase shift between the applied volt- age and the bemf is required in order to optimize the system efficiency (the loss in efficiency is related to the cosine of the angle between bemf and current). via the spi it is possible to set an appropriate torque optimizer (to) value based on the application characteristics (rm, lm, speed). when a zc is detected the circuit starts scanning the stored smooth drive wave shape (or the traditional six step profile) from the number of sample pointed by the to register; the tri-stated window is opened a certain number of samples before. in the following table the relation between the to register contents and the window and masking time position and duration: start stop window to-w at zc detection mask to-w to-w+m set load coarse phase write reg.07h loadcp = 1 (*1) wait loop (300 usec) start sync. to smoothdrive commutation i=0 wait rising edge of zc (pin 22) exit sync. to smooth drive commutation set load coarse phase write reg.07h loadcp = 1 (*2) no i = 2 yes no yes set clcoast write reg.03h spstate[3:0]=0000 motor running in sine or six set closed loop sine write reg.03h spstate[3:0] =0111 set closed loop six write reg.03h spstate[3:0] =0110 sine six (*5) (*6) (*7a) (*7b) time out control no start up failure exit yes set olcoast write reg.03h spstate[3:0]=0001 wait loop (30 usec) zc_samplingroutine begin zc_samplingroutine end reset time out reset time out (*3) (*4) inc i call zc_samplingtime routine call zc_samplingtime routine
L7250 26/46 2.8 spindle pwm current limiting peak motor current is limited with a fixed frequency pwm scheme that works in conjunction with the smooth- drive pwm rate. when the current limit threshold is reached the motor is put in brake condition, and it is re- enabled at the beginning of the next pwm cycle if the current limiting condition is false. spindle current is sensed via an external resistor connected from the low side driver sources to ground. this sense voltage is compared to an internal programmable voltage reference (reg04h currdac[2:0]). there is a built in digital filter, generating a sysclk derived delay (20 * sysclk period) from the over current event. this delay appears on both edges of the current limiting comparator. 2.9 slew rate control closed loop voltage slew rate control is provided on both edges for the high and low side drivers. the slew rate value can be set with three bits in the serial port (reg04h spslew[2:0]). slew rates up to 80v/us and down to 10v/us will be controllable. 2.10 synchronous rectification the appropriate low-side driver is enabled during the off-time phase to conduct recirculation current with a lower voltage drop than the low side driver body diode, reducing power losses. crossover current protection is pro- vided to prevent shoot-through currents. 2.11 open loop and closed loop brake spindle braking may be done while keeping the smoothdrive system in sync with the motor, or not. closed loop braking means zc's are still being detected in the same way as when normally commutating. so, all 3 motor phases are driven low, but when the window is normally opened to look for a zc, motu is tri-stated. when the zc occurs, motu is driven low as the other motor phases, until the next window comes up. a mo- tionless motor will wait for a zc, keeping motu tri-stated and the other two phases low. open loop braking means that all 3 motor phases are driven low, and zc's are not detected. braking caused by a power fault is always open loop braking. cbrk provides control voltage for brake circuitry after power fails. an external cap on this pin is charged to 5v, so that the cap stays charged after a power failure.
27/46 L7250 3 voice coil motor driver the vcm driver is configured as a transconductance amp, with an n-channel dmos h-bridge power output, current sense amp, error amp, and 15 bit linear dac for command input. the power stage is a class ab voltage amp. the error amp closes the transconductance loop around the power amp, using feedback from the current sense amp. the vcm block is shown below. figure 7. vcm driver block diagram the current flowing into the voice coil is equal to: where g s is the sensing opamp gain (programmable via serial port considering a typical application where rf = 5.6k, ri = 2.5k, rs = 0.25 w and gs = 4.5v/v we obtain a maximum current equal to about 2a for 1v dac output (vin). the sense amplifier input range is about 0.55v. the power stages assure this current requirement and they have a differential gain of 16. the loop is compensated through the rc network rc and cc that cancels out the motor pole lm/rm. this graphic shows the theoretic gloop bode diagram and put in evidence the second pole of the loop that is strictly related to the error amplifier bandwidth. figure 8. gloop vm/2 vm/2 38 39 37 vm vm 3/4 5/6 42 41 40 dac 15 dacref agnd vcmp vcmn dacref dacref dacref dacref vcm gnd senseamp erroramp vcv vcm gnd 43/44 45/46 52/53 tristate tristate s1 s2 1/2/54/55 por rc cc ri rf gs gpow gpow rs rm lm i coil r ? r i ------ C 1 r s g s ---------------- - v in = fdt error closed loop r c r f ----- - 1 r c c c ---------------- - 1 r f c c ---------------- w t r f r i r c r f r i + () --------------------------------- 2g pow r s g s r s r m + -------------------------------------- 1 r f c c ---------------- gloop a 0 r i r i r f + ----------------- a 0 2g pow r s g s r s r m + ------------------------------------------------- r i r i r f + ----------------- w t r i r i r f + -----------------
L7250 28/46 considering a typical application with rs = 0.25 w , lm = 0.75mh, rm = 7.5 w , gs = 4.5 gpow = 8, rf = 5.6k, cc = 3.3nf, rc = 33k we will obtain a bandwidth about 20khz. to increase the bandwidth a different values of the external components could be calculated following the above relation and taking in account the limitation introduced by the second pole due to the error amplifier bandwidth ( w t). this one has a typical value about 4mhz. 3.1 vcm operating modes and control at power-on-reset the vcm register is cleared and the vcm is in unload/retract mode. via serial port is possible to command the following modes: unload/retract, tri-state (disable), brake, enable current mode, enable voltage mode, offset calibration 3.2 vcm power driver h-bridge the vcm driver is capable of high performance linear, class-ab, h-bridge operation with all power devices in- ternal. the power amp stage is configured as a voltage amp with gain of 16. the h-bridge consists of 4 n-chan- nel dmos power transistors. power is supplied to the h-bridge through the internal iso-fet ( at pins vm 52,53), and ground returned via four vcmgnd pins (5,6,43,44). boosted gate drive for the high side drivers is provided by the charge pump circuitry, with the boosted voltage at the vcp pin. 3.3 vcm current command 15 bit dac the vcm current command is defined by an internal linear, 2's complement, 15 bit dac. the mid scale refer- ence for the dac, vref25, is defined by an on-chip reference at 2.5v. vref25 is the reference for the sense amp and error amp in the vcm loop. level shifting from vref25 to vm/2 will be done in the power stage. 0x3fff max current flowing from vcmn to vcmp (current mode operation) 0x---- 0x0001 0x0000 zero current 0xffff 0x---- 0x4000 max current flowing from vcmp to vcmn (current mode operation) to write the 15 bit dac the two register reg09h [14:8] and reg0ah [7:0] have to be referred. at any time the msb register is entered, to apply the modification also the lsb register must be write. instead writing only the lsb register its content will be immediatly visible on the dac structure. then a double write sequence its necessary if the [14:8] bit have to be modified while it is possible to move the dac in a fine way (write of the [7:0] bit) with only one write sequence. 3.4 vcm current sense amp vcm current is sensed by a diff amp that amplifies and level shifts the voltage drop across an external resistor in series with the vcm coil. the sense amp has a nominal differential voltage gain programmable through the serial port bit reg09h bit 7, and the output, vsense, is relative to vref25 (pin 21). the amp has been design to have high common mode rejection (over 70db at dc), power supply rejection over 60db, and as low an input offset as possible. 3.5 vcm current loop error amplifier the vcm error amp gains up the difference between the current command voltage dac_out and the current sense voltage vsense. vcm current loop compensation is implemented externally with an rc network con- nected across err_in and err_out. the error amp output is referred to vref25. 3.6 error amp output clamp the error amp output swing is clamped in both directions (vref25+/-3vbe) to prevent wind-up of the integrating compensation components around the error amp in the event of saturation.
29/46 L7250 3.6.1 voltage mode in voltage mode, the vcm power outputs will apply a voltage to the vcm motor commanded by the vcm dac. this is implemented by tristating the sense amp and error amp outputs, and connecting dac_out to err_out with an internal switch (switch s2). skipping the err_out amplifier the dac command will enter the power section without any inversion, then the dac codification must be considered in opposite direction respect to the current mode operation. 3.7 vcm loop offset calibration mode the vcm loop calibration mode can be implemented following two different approach: 1) the vcm loop is enabled (sense amp, error amp, dac), but the vcm power stage is tri-stated. thus, the sense amp is guaranteed to be monitoring a zero current condition. to implement offset calibration, the current command is swept through zero by the controller asic. since the gm loop is open, the error amp output will be saturated in one direction or the other depending on the current command (to configurate the error opamp as a comparator the external compensation network will be disconnected opening the switch s1). as the command sweeps through the zero current command point, the error amp output will swing to the other extreme. the comparator senses the out- put swing of the error amp, and through the serial port (reg. 00h -> b6) interrupts the asic. the ap- propriate dac value corresponding to the trip point interrupt is the loop zero current offset. figure 9. vcm current loop offset calibration 1 set vcm offset calibration write reg.03h vcmstate[2:0] = 101 start vcm current loop offset calibration routine update 15 bit dac write reg.09h dac[14:0]= dac_val exit vcm current loop offset calibration routine select sense amplifier gain 4.5 v/v 16 v/v dac_val = 0 flag1 = 0 , flag2 = 0 set senseampl.gain write reg.09h gainsw bit = 0 set senseampl.gain write reg.09h gainsw bit = 1 read error ampl output read reg.00h vcmcalout bit value vcmcalout = 0 no yes dac_val = dac_val +1 flag2 =1 flag1 = 1 flag1 = 1 dac_val = dac_val -1 flag2 = 1 yes no yes no store the dac_val as the zero loop offset * dac_val is in 2 complement format
L7250 30/46 2) a second approach is considering to have the vcm in stop position; to enable it in current mode con- figuration driving current in the right direction in order to be sure to mantain the stop position; to decre- ment the 15bit dac value to reach the zero current condition using the 10bit adc to measure the current value. in the following diagram a detailed flow chart is presented. figure 10. vcm current loop offset calibration 2 set vcm in tristate write re g .03h vcmstate[2:0] = 001 start current mode zero iout calibration routine set 15bitdac to have vcm current with no motion write re g .09h & re g .0ah dac[14:0] = dacvalue set the gainsw to high or low set vcm in en.current mode write re g .03h vcmstate [2:0] = 011 call ioutdi g italval routine polarity check adc_data[9] = 0 fla g _a=0 exit current mode zero iout calibration routine ye s no fla g _a=0 dacvalue=1200 ( 0x4b0 ) note 1 dacvalue-=1 dacvalue<-1200 exit with error 1 calibration not performed positive offset to bi g ye s no start 10bit adc conversion of the iout channel write re g .0ch adc_ch_addr[1:0] =00 adc_start=1 exit ioutdi g italval routine wait end of conversion read 10bit adc read re g .0bh adc_data[9:2] read re g .0ch adc_data[1:0] yes no start ioutdi g italval routine update the 15bitdac write re g .09h & re g .0ah dac[14:0] =dacvalue iout yes store dacvalue as reference for zero iout no fla g _a=1 exit with error 2 calibration not performed ne g ative offset to bi g wait 20 msec call ioutdi g italval routine iout_offset = adc_data[9:0] note 2 note 1 : once the vcm will be enabled in current mode with the dac value at 1200 the current will keep the motor a g ainst the crash stop position note 2 : with the vcm in tristate, the result of the di g ital conversion of the iout channel has to be used as zero current offset value adc_data[9:0] -= iout_offset ( subtract the offset )
31/46 L7250 3.8 vcm ramp load / unload system figure 11. the ramp load system is designed to allow a microcontrolled assisted constant velocity for ramp loading and unloading. vcm current-voltage-bemf monitor circuitry is integrated for the loading or unloading operation. vcm current- voltage-bemf are converted in digital by a 10 bit ad converter and can be read through the serial port. 3.8.1 load/unload operation at power good when both the 12v and 5v are present, the load/unload operation can be assisted by the microcontroller. the power stage can be driven in both current and voltage mode and the velocity of the load/unload operation is controlled by reading the internal registers that give information regarding the vcm current, voltage and the bemf generated by the vcm motion. the vcm current measurements is done by sending to the ad converter the output of the vcm current sense ampl. the vcm voltage is measured by connecting an operational amplifier, with a scaling factor, to the vcmp and vcmn of the power stage. the vcm bemf detection is done using a first amplifier, having a controlled gain, followed by a second opera- tional amplifier implementing the transfer function necessary to bemf reconstruction. the programmable gain of the first operational amplifier it is necessary to consider various coil resistance values related to different ap- plication. the bemf information is carry out on pin vcmbemf (31) for filtering pourpose (the output impedance is typi- cally set to 500ohm). the conversion in digital of these parameters is used by the microcontroller as a feedback to close the velocity control loop during the ramp loading or unloading operation, and to perform calibrations. all these signals can enter directly the adc block (adcrange bit = 0) or can be scaled to adjust the dynamic range to the adc one (adcrange bit = 1). the scaling factor is set equal to 2.25 for the current, voltage, auxiliary input channels, while is set to 1.25 for the bemf input channel. rs vcmn vcm vcmp +a -a + _ + _ + _ _ + current adc 10 bit voltage bemf sel&start gain calibration procedure vcm predriver (sense ampl) to serial port offset calibration vga calcoarse 29 vcontrol 5 msb from adc fine calibration bit from serial port
L7250 32/46 3.8.2 gain calibration procedure the bemf detector circuitry must be calibrated right before the beginning of any load/unload operation. because the coil resistance can vary up to 30% due to thermal effects, it is necessary to calibrate the gain of the first stage depending on the ratio between the operating coil resistance value and the sense resistance val- ue. the output of the bemf detector circuiry is: bemf = outp - outm - rs*ivcm ( 1+ rm/rs) where: rm = motor resistance rs = sensing resistance if the gain of the first stage is matching the ratio between the coil resistance at operating temperature and the sense resistor, the bemf measured is right the value generated by the vcm motion. the gain trimming is done with the vcm in a stop position (no bemf must be generated) with a certain amount of current flowing into the coil; in this condition the gain must be adjusted in order to have zero voltage from the bemf circuitry. the gain adjusting is splitted in two phases. a coarse calibration is obtained setting the external resistor divider at the calcoarse pin (29) following the relation: vcontrol = [0.21 + (rm/rs) / 28.8] vcontrol max. range = vbg 0.75v where: vbg = bandgap voltage (typ = 1.25) a fine calibration is obtained by writing the internal register 02h -> b[3:0]. the fine calibration is used to com- pensate the variation of the vcm coil resistance according with operating temperature condition. the calibration is implemented moving the vcontrol voltage by a percentage indicated on the rlcal table at pag.17. 3.8.3 vcm bemf offset trimming due to the high gain necessary to implement the bemf reconstruction, the inpact of the offset on the output value is very high. for this reason dedicated circuitry, using the 5 msb of the ad converter, has been integrated in order to compensate this offset. the flow chart below reported are describing the method to implement the offset calibration.
33/46 L7250 figure 12. vcm bemf offset calibration clear routine set vcm in tristate write reg.03h vcmstate[2:0] = 001 start vcm bemf offset calibration clear routine set preadc in sleep write reg.06h preadc[1:0] = 00 read 10bit adc read reg.0bh adc_data[9:2] =00000000 (reset value) read reg.0ch adc_data[1:0] =00xxxxxx (reset value) latch offset compensation write reg.03h bemfoffcal = 1 then bemfoffcal = 0 set adc clock write reg.06h preadc[1:0] = 01 exit vcm bemf offset calibration clear routine optional reset rm/rs fine calibration write reg.02h rlcalib[3:0] = 0000
L7250 34/46 figure 13. vcm bemf offset calibration routine at the end of the calibration routine the analog value measured at pin 31 is rapresenting the vcm bemf value at the zero motion (bemf zero value). with the adc it is possible to operate a new convertion in order to mem- orize this value and to take in account of it during the load/unload procedure. 3.8.4 power off unload - active brake and constant voltage unload operation in case of power shut down, an unload procedure start automatically in order to take the heads over the ramp in the parking position (the same procedure can be also enabled, when the power is on, via serial port program- ming the unload/retract status of the vcm -> reg. 03h. in this case at the end of the unload phase the spindle motor is driven in tri-state condition). the unload procedure doesnt start at power off if the vcm status bit are set to 000 because the system is con- sidering the heads already in park position. no entering the unload procedure also the spindle brake is not ac- tivated. the unload procedure is done in two step: - active brake - constant voltage unload operation the unload procedure take place only if the vcm status bit have moved from the 000 configuration. otherwise the unload procedure doesn't start and in case of power shut down the spindle motor enter the brake condition. active brake : it is used to have a fast recovery of the vcm velocity down to the unload programmed velocity. if just before a power shut down a fast seek was commanded, it is necessary to recover the vcm velocity in set vcm in tristate write re g .03h vcmstate[2:0] = 001 start vcm bemf offset calibration routine set adc clock write re g .06h preadc[1:0] = 01 start 10bit adc conversion of the bemf channel write re g .0ch adc_ch_addr[1:0] =10 adc_start=1 exit vcm bemf offset calibration w ait end of conversion read 10bit adc read re g .0bh adc_data[9:2] read re g .0ch adc_data[1:0] yes no optional latch offset compensation write reg.03h bemfoffcal = 1 then bemfoffcal = 0 to restart this routine is mandatory to start first the clear routine (see fig. 10)
35/46 L7250 order to avoid to rise the ramp or to meet the id crash stop at high speed. the over velocity detector circuit consist in a window comparator; in case of power failure the vcm power stage is tri- stated (for a fixed time about 200 m s) in order to detect the amplitude of the bemf generated by the vcm motion. if the vcm bemf is out of the window of the over velocity detector (this means that the heads are travelling at high speed versus the inner or outer position), the active brake routine is invoked. the voltage threshold ( = motor electrical constant * motor angular velocity), setting the over velocity detector window, is set internally to 1.1v (to 0.4v if 5v application is considered). at the contrary, if the vcm speed is inside the window (the heads where on track or moving slowly) the active brake is skipped and the constant unload operation is commanded. the active brake routine consist in a procedure that drive the vcm alternately with two steps: - first activating the diagonal of the power stage in order to drive current in the right direction to slow down the speed of the vcm for a time (rltonbrake) that is half of the programmed rltoffbrake. - then activating both the low side drivers of the power stage putting the vcm in short brake condition for a pro- grammable time (rltoffbrake). with the vcm in short brake the current into the coil is forced by the bemf generated by the motion of the motor and the sense amplifier output is sensed in order to detect indirectly the vcm speed. the switch between the active brake routine and the constant voltage unload operation is done when the vcm current, measured at the sense amplifier output during the short brake condition, fall down to zero (vcm is stopped). the rltoffbrake (and so the rltonbrake) time can be programmed by writing the reg. 02h. the active brake procedure can enabled/disabled by writing the reg. 01h. in case the active brake procedure is disabled, at power off the constant unload operation start immediately. constant voltage unload operation : a constant voltage (with a sink and source capability) is applied to the vcm in order to drive the heads over the ramp in the parking position. according with the contents of the registers reg. 01h it is possible to perform the unload operation in one or two steps and for each steps to select the voltage level applied to the vcm. the capacitor connected at the timer1 (pin 28) define the total time of the unload operation ; during the unload operation this capacitor is discharged by un internal constant current generator. programming the bit b3b2b1 of the reg. 01h it is possible to select different unload procedures: with these bit set to 000 the unload is done in one step with the voltage selected by the two bit rlvoltage1 of reg. 01h. with these bit set to 111 the unload is done in one step with the voltage selected by the two bit rlvoltage2 of reg. 01h. the spindle motor is tristated during the unload operation the other combinations of the bit b3b2b1 defines different threshold for the comparison with the discharging voltage of the capacitor at pin 21 . the timing for the first step is with the capacitor voltage greater then the programmed threshold, the timing for the second step start when the capacitor voltage is below the threshold and end when the capacitor is dis- charged under the 'end unload threshold' (0.2v typ) . in all the cases, when the capacitor at pin 21 is discharged under the 'end unload threshold' the spindle motor is driven inbrake condition . the typical value of the retract procedure timing can be extimated using the following expression: t = tstep1 + tstep2 = 1.15 * c ext where: cext = external capacitor at pin timer1 (28) measured in uf
L7250 36/46 figure 14. costant voltage retract operation at power down figure 15. two step unload temporization constant volta g e r etract o peration check npor status hi g h low check vcm active brake proc. re g .01h -bit[0] disabled enabled g et r ltim er[2 :0 ] read re g .01h rltimer[2:0] = 000 start only unload1 with the selected rlvolta g e1 no rltimer[2:0] = 111 start only unload2 with the selected rlvolta g e2 yes no start unload1 + unload2 with the selected rlvolta g e1 & rlvolta g e2 start the vcm active brake procedure end (*) set spindle powers in tristate wait end of rltim er set spindle powers in brake voltage capacitor pin 21 time step 1 step 2 por programming threshold end unload threshold
37/46 L7250 3.8.5 constant voltage unload operation at power on the same costant voltage retract operation can be activated via software (during a power on phase). in that case no actions are implemented to the spindle motor; the spindle motor will continue to mantain its running status. again in power on condition if the bit b3b2b1 of the reg. 01h are set to 000 or 111 only one step costant volt- age retract is activated as in power off condition with the difference that when the end unload threshold is reached the retract voltage is mantained applied to the motor until a different programmation is asserted via se- rial port by the microcontroller. in all the others b3b2b1 combination as the timer1 is elapsed the vcm is put in tristate condition. note: in case of hard disk application with css operation (no ramp loading), the polarity of the vcm connection must be re- versed. in this way the active brake and the constant voltage unload operations will force the heads in the inner position of the disks. 3.9 10 bit ad converter the L7250 device includes a 10 bit analog to digital converter (hereafter adc). the adc uses a two complement output code. the adc converts one of four different channels on demand, through spi, and result of conversion can be read from spi too. the uc tells the adc which channel must be converted, gives a start signal, reads the conversion result; all this happens through the spi. the adc convertion frequency, then its conversion time, could be changed using two bits into the serial port (reg 06h -> b1,b2). setting these two bit to the configuration 00 the adc can be disabled entering a sleep mode status. hereafter is listed the recommended sequence of operations to obtain a conversion from adc: a) m c selects which channel must be converted, writing the adc_ch_addr field in spi (reg 0ch -> b1,b2); m c selects the adc input range writing the adcrange bit (reg 0ch -> b3); m c writes high the adc_start bit (reg 0ch ->b0) in spi (end of required conversion automatically resets it); b) now m c can read the conversion result from the spi registers; c) a new conversion can be required. the m c isn't allowed to require a conversion start when the adc is already running; the start bit can be written anyway, but adc logic ignores it and continues the current conversion. if the uc avoids modifies over the adc_start bit, it can be used as a flag to state the end of the conversion. the result of conversion is ten bits wide, larger than the 8 bits spi registers, so it has been spanned over two registers; if allowed by the precision required for the application, only the 8 msbits can be read with a single spi read operation, saving some time. a new conversion can be required after the end of the previous one but before the read-back of the result, i.e. swapping the order of (b) and (c) points listed before; working this way, it's possible to convert values closer in time than with the previous sequence. spi includes an additional read-only field (2bits) that contains the channel number related to the present con- version result.
L7250 38/46 4 power monitor, voltage regulators and shock sensor 4.1 npor - power on reset the power on reset circuit monitors 12v and 5v power supplies as well as 3.3v and 2.5v regulators. if any monitored voltage falls below its under voltage threshold, npor is latched low after an internal glitch filter delay. when the positive regulators are in position, a delay time is added, the por delay, before npor goes high and the reset condition is cleared. during this delay time, any power fault will reset the por delay and start the process over again. t delay = 0.520 * c ext where : c ext = external capacitor on pin cpor measured in uf. 4.2 linear voltage regulators:1.8v & 3.3v the 3.3v linear use an external npn transistor connected to the 5v power supply line, instead the 1.8v linear regulator use an external npn transistor that could be connected to the 3.3v line or to the 5v power supply line. to fix the 1.8v regulator voltage output an external resistor divider as to be used. the regulated voltage could be varied around the 1.8v value (from 1.3v to 2v) choosing the external divider appropriately. the stability of the two regulators is guarantee by the external filter capacitor . the internal vbg reference is trimmed at the wafer level. figure 16. linear positive regulators vb g 15 16 r2 r1 33_base 33_feed vcc5 vb g 13 14 r2ext r1ext 25_base 25_feed vcc5 1.8v output 3.3v output cext cext
39/46 L7250 4.3 negative voltage regulator (flyback configuration) this is the default negative voltage regulator configuration; programming the test register is possible to re- configurate this regulator following the indication present on the next paragraph. the negative voltage regulator is a fixed frequency switcher intended to provide bias for the mr head preamp. the nvr consists of an internal triangular wave oscillator, an error amplifier, a comparator and a circuitry to soft start_up the regulator itself, in conjunction with an external pmos power device, power diode, inductor, capac- itor, feedback resistors and compensation network (refer to the block diagram of the negative voltage regulator including also the external components). the error amp compares the external voltage feedback to the internal reference (vbg = 1.25v). the voltage dif- ference value is scaled by two external resistors. the ratio of these two resistors determines the nominal value of the regulated negative voltage (the internal reference is set to the bandgap voltage ~1.25v). the error am- plifier input is available at n_feed pin and the amplifier output is available at n_comp pin. the voltage error gain and the loop compensation can be adjusted by the external components across these two pins. the output of the error amplifier is compared to an internal triangular wave oscillator to determine the duty cycle of the ex- ternal pmos power switch. a voltage clamp is placed on the error amplifier output to limit the maximum duty cycle. the nominal value of the triangular wave oscillator frequency is 500 khz (programming the test register reg 0fh to 00001001 it is possible to increment the switching frequency to the nominal value of 1mhz). during the on portion of the duty cycle, the pmos charges an external inductor. during the off phase, the inductor charges a capacitor through an external diode, in a voltage inverter configuration. this architecture avoids any negative voltage on the L7250 ic pins. under normal specified load conditions and correct scaling of the ex- ternal components the regulator circuit should operates in a constant frequency variable duty cycle switch mode without any cycle slips. the nvr include also a digital soft start_up circuitry in order to limit the in rush current coming from the power supply when the regulator is turned-on. the nvr is controlled via serial port (using the reg. 05h -> b1 the regulator could be turned on and off). during the power-up and power-down phases the regulator is always off being the serial port in reset status then the vnegen bit equal to zero. during those phas- es the n_drv output driver is in tri-state condition then an external pull-up to assure the pch off condition must be considered. figure 17. negative regulator (flyback configuration) - default configuration 12 n_comp 10 n_drv vcc5 21 vref25 vbg (typ 1.25) 11 n_feed r1ext m1ext r2ext rcext ccext cfext 500khz - 1mhz 5k
L7250 40/46 4.4 negative voltage regulator (cuk configuration) programming the test register reg 0fh to 00101001 it is possible to re-configurate the negative regulator loop inverting its polarity. all the others test register (reg0fh) configurations are resetting to the default nega- tive voltage regulator loop polarity (take care to avoid the test register bits modification if the cuk configuration hardware is present and the negative regulator is enabled) . the functionality of the regulator is the same descripted on the previous paragraph with the difference that the loop polarity is reversed to permit to drive the external nch component. during this operation the nominal value of the triangular wave oscillator frequency is always fixed to 1 mhz. the nvr is controlled via serial port (using the reg. 05h -> b1 the regulator could be turned on and off). take care to program correctly the test register to enter the cuk configuration before to enable the nvr. during the power-up and power-down phases the regulator is always off being the serial port in reset status then the vnegen bit equal to zero. during those phases the n_drv output driver is in tri-state condition then an ex- ternal pull-down to assure the nch off condition must be considered. figure 18. negative regulator (cuk configuration) - test register => 00101001 12 n_comp 10 n_drv vcc5 21 vref25 vbg (typ 1.25) 11 n_feed r1ext m1ext r2ext rcext ccext cfext 1mhz c1ext 5k
41/46 L7250 4.5 shock sensor this block takes input from a piezoelectric or charging mode shock sensor element (selectable using the spi bit shockconf -> reg02h, bit 7 ), and includes external filtering capability. a digital latched signal is available on skdout pin if the sken bit (from spi) is set to 1 otherwise the skdout pin is transparent to the shock signal. if the output signal has been latched, a pulse to zero of the sken bit it is necessary to clear it. the shock sensor element will be connected to the skin and vref25. figure 19. piezoelectric shock sensor typical application block diagram (reg02h->bit7=0) figure 20. charging shock sensor typical application block diagram (reg02h->bit7=1) 24 skout 26 skfout 25 skfin vref25+vthh vref25-vthl 0 1 s r 27 skdout 21 vref25 23 skin r 9r vref25 sken (from spi) r1ext c1ext c2ext r2ext 10m 24 skout 26 skfout 25 skfin vref25+vthh vref25-vthl 0 1 s r 27 skdout 21 vref25 23 skin vref25 sken (from spi) r1ext c1ext c2ext r2ext vref25 csext rsext rg2ext rg1ext
L7250 42/46 4.6 over temperature protection L7250 has a temperature protection circuit consisting of a temperature sense circuit and two comparators. the temperature sense circuit generates a voltage proportional to the absolute die temperature. one comparator trips when the die temperature exceeds 140 deg c, asserting the temperature warning signal in the status reg- ister (thwarn in the reg 00h -> b3). the thermal warning comparator has nominally 20 deg c hysteresis. the thermal shutdown comparator trips when the die temperature exceeds 160 deg c, indicates an over tem- perature condition in the status register (thshutdown in the reg00h -> b4). the status register is transparent to the thermal shutdown information. if the thshutdown bit is equal to zero only the flag on the status register is activated, else the L7250 is driven into thermal shutdown mode, which initiates unload of the voice coil motor (no actions on the spindle motor has been taken). hysteresis of 25 deg c on this comparator allows the die temperature to stabilize before it is re-enabled. iif the thshutdown bit is set to 1, the thermal shutdown condition is latched, then to re-enable the function a reset cycle is needed (thshutdown bit must be programmed to 0, then set again to 1).
43/46 L7250 figure 21. 12v application diagram 100nf vmot spindle motor ct u v w 12v 100nf 22nf 330nf 56 57 58 59 60 61 62 63 64 49 50 51 52 53 54 55 47uf 0.22ohm vcm_p vcm motor 0.27ohm 46 47 48 vcm-p vcmn2 rsen1 rsen2 r s e n s e o u t w 1 o u t w 2 v m 1 v m 2 v c v 4 v c v 3 c t o u t v 1 o u t v 2 r s e n 3 r s e n 4 o u t u 1 o u t u 2 v b o o s t c p o s c h 1 2 3 vcmp1 vcm-p vcv1 vcv2 10uf 100nf 5v * default 5v s g 5k 4 5 6 7 8 9 vcmp2 vcc5 dig_gnd vcmgnd1 vcmgnd2 cposc L7250 sns_out sns_p sns_n vcmn1 vcmgnd3 vcmgnd4 40 41 42 43 44 45 vcm_m sclk data sysclk 34 35 36 37 38 39 sclk sdata dac_out err_out err_in sysclk tqfp 64 10x10 10 11 12 13 14 15 n_drv n_feed n_comp 25_base 25_feed 33_base d gnd -4v configuration 5v 16 33_feed 17 18 19 20 21 22 23 24 25 c p o r n p o r c b r a k e a g n d v r e f 2 5 z c s k i n s k o u t s k f i n 26 27 28 29 30 31 32 t i m e r 1 t e s t s k f o u t s k d o u t a d a u x v c m b e m f c a l c o a r s e 33 sen sen zc test1 npor shockout aux input 22nf 1uf 220nf 100nf 5v 10uf 275ohm 625ohm gnd 1.8v 100nf gnd 3.3v 100nf 10uf shock sensor
L7250 44/46 figure 22. 5v application diagram 100nf vmot spindle motor ct u v w 1 2 vboost 22nf 5v 100nf 22nf 330nf 56 57 58 59 60 61 62 63 64 49 50 51 52 53 54 55 47uf 0.22ohm vcm_p vcm motor 0.27ohm 46 47 48 vcm-p vcmn2 rsen1 rsen2 r s e n s e o u t w 1 o u t w 2 v m 1 v m 2 v c v 4 v c v 3 c t o u t v 1 o u t v 2 r s e n 3 r s e n 4 o u t u 1 o u t u 2 v b o o s t c p o s c h 1 2 3 vcmp1 vcm-p vcv1 vcv2 100nf 4.7uf * default 5v s g 5k 4 5 6 7 8 9 vcmp2 vcc5 dig_gnd vcmgnd1 vcmgnd2 cposc L7250 sns_out sns_p sns_n vcmn1 vcmgnd3 vcmgnd4 40 41 42 43 44 45 vcm_m sclk data sysclk 34 35 36 37 38 39 sclk sdata dac_out err_out err_in sysclk tqfp 64 10x10 10 11 12 13 14 15 n_drv n_feed n_comp 25_base 25_feed 33_base d gnd -4v configuration 5v 16 33_feed 17 18 19 20 21 22 23 24 25 c p o r n p o r c b r a k e a g n d v r e f 2 5 z c s k i n s k o u t s k f i n 26 27 28 29 30 31 32 t i m e r 1 t e s t s k f o u t s k d o u t a d a u x v c m b e m f c a l c o a r s e 33 sen vboost r5en 20k sen zc test1 npor shockout aux input 22nf 1uf 220nf 100nf 5v 10uf 275ohm 625ohm gnd 1.8v 100nf gnd 3.3v 100nf 10uf shock sensor
45/46 L7250 tqfp64 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.18 0.23 0.28 0.007 0.009 0.011 c 0.12 0.16 0.20 0.0047 0.0063 0.0079 d 12.00 0.472 d1 10.00 0.394 d3 7.50 0.295 e 0.50 0.0197 e 12.00 0.472 e1 10.00 0.394 e3 7.50 0.295 l 0.40 0.60 0.75 0.0157 0.0236 0.0295 l1 1.00 0.0393 k 0 (min.), 7 (max.) a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.10mm outline and mechanical data
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